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SM90 (Hopper) Instructions

150 base instructions, 812 total variants

ACQBULK
Wait for Bulk Release Status Warp State
1
AL2P
Unknown op
unknown
ALD
Unknown op
unknown
ATOM
Atomic Operation on Generic Memory
10
ATOMG
Atomic Operation on Global Memory
10
ATOMS
Atomic Operation on Shared Memory
6
B2R
Move Barrier To Register
3
BMMA
Bit Matrix Multiply and Accumulate
2
BMSK
Bitfield Mask
5
BREV
Bit Reverse
5
CGAERRBAR
CGA Error Barrier
1
CS2R
Move Special Register to Register
1
CSMTEST
Unknown op
unknown
DADD
FP64 Add
5
DFMA
FP64 Fused Mutiply Add
9
DMMA
Matrix Multiply and Accumulate
2
DMUL
FP64 Multiply
5
DSETP
FP64 Compare And Set Predicate
5
ELECT
Elect a Leader Thread
2
ENDCOLLECTIVE
Reset the MCOLLECTIVE mask
1
ERRBAR
Error Barrier
1
F2FP
Unknown op
unknown
F2I
Floating Point To Integer Conversion
4
F2IP
FP32 Down-Convert to Integer and Pack
9
FADD
FP32 Add
5
FCHK
Floating-point Range Check
5
FFMA
FP32 Fused Multiply and Add
9
FLO
Find Leading One
5
FMNMX
FP32 Minimum/Maximum
10
FMUL
FP32 Multiply
5
FOOTPRINT
Unknown op
unknown
FRND
Round To Integer
5
FSEL
Floating Point Select
5
FSET
FP32 Compare And Set
5
FSETP
FP32 Compare And Set Predicate
5
FSWZADD
FP32 Swizzle Add
1
GETLMEMBASE
Get Local Memory Base Address
1
HADD2
FP16 Add
6
HFMA2
FP16 Fused Mutiply Add
36
HMMA
Matrix Multiply and Accumulate
4
HMNMX2
FP16 Minimum / Maximum
10
HMUL2
FP16 Multiply
5
HSET2
FP16 Compare And Set
5
HSETP2
FP16 Compare And Set Predicate
5
I2F
Integer To Floating Point Conversion
5
I2FP
Integer to FP32 Convert and Pack
5
I2I
Integer To Integer Conversion
5
I2IP
Integer To Integer Conversion and Packing
5
IABS
Integer Absolute Value
5
IADD3
3-input Integer Addition
10
IDP
Integer Dot Product and Accumulate
4
IMAD
Integer Multiply And Add
50
IMMA
Integer Matrix Multiply and Accumulate
4
IMNMX
Integer Minimum/Maximum
5
IPA
Unknown op
unknown
ISBERD
Unknown op
unknown
ISETP
Integer Compare And Set Predicate
10
LD
Load from generic Memory
8
LDC
Load Constant
4
LDG
Load from Global Memory
8
LDGDEPBAR
Global Load Dependency Barrier
1
LDGSTS
Asynchronous Global to Shared Memcopy
4
LDL
Load within Local Memory Window
6
LDS
Load within Shared Memory Window
4
LDSM
Load Matrix from Shared Memory with Element Size Expansion
4
LDTRAM
Unknown op
unknown
LEA
LOAD Effective Address
22
LEPC
Load Effective PC
2
LOP3
Logic Operation
5
MATCH
Match Register Values Across Thread Group
2
MOV
Move
5
MOVM
Move Matrix with Transposition or Expansion
1
MUFU
FP32 Multi Function Operation
5
NOP
No Operation
1
OUT
Unknown op
unknown
P2R
Move Predicate Register To Register
5
PIXLD
Unknown op
unknown
PLOP3
Predicate Logic Operation
14
PMTRIG
Performance Monitor Trigger
1
POPC
Population count
5
PREEXIT
Dependent Task Launch Hint
1
PRMT
Permute Register Pair
9
QSPC
Query Space
4
R2P
Move Register To Predicate Register
5
R2UR
Move from Vector Register to a Uniform Register
1
REDAS
Asynchronous Reduction on Distributed Shared Memory With Explicit Synchronization
2
REDUX
Reduction of a Vector Register into a Uniform Register
1
RPCMOV
PC Register Move
10
S2R
Move Special Register to Register
1
S2UR
Move Special Register to Uniform Register
1
SEL
Select Source with Predicate
5
SETCTAID
Set CTA ID
1
SGXT
Sign Extend
5
SHF
Funnel Shift
9
SHFL
Warp Wide Register Shuffle
4
STAS
Asynchronous Store to Distributed Shared Memory With Explicit Synchronization
2
SUATOM
Atomic Op on Surface Memory
8
SULD
Surface Load
8
SUQUERY
Unknown op
unknown
SYNCS
Sync Unit
15
TEX
Texture Fetch
12
TLD
Texture Load
12
TLD4
Texture Load 4
12
TMML
Texture MipMap Level
12
TXD
Texture Fetch With Derivatives
12
TXQ
Texture Query
5
UBLKCP
Bulk Data Copy
2
UBLKPF
Bulk Data Prefetch
2
UBLKRED
Bulk Data Copy from Shared Memory with Reduction
2
UBMSK
Uniform Bitfield Mask
2
UBREV
Uniform Bit Reverse
2
UCGABAR_ARV
CGA Barrier Synchronization
1
UCGABAR_WAIT
CGA Barrier Synchronization
1
UCLEA
Load Effective Address for a Constant
2
UF2FP
Uniform FP32 Down-convert and Pack
4
UFLO
Uniform Find Leading One
2
UIADD3
Uniform Integer Addition
8
UIMAD
Uniform Integer Multiplication
10
UISETP
Integer Compare and Set Uniform Predicate
4
ULDC
Load from Constant Memory into a Uniform Register
6
ULEA
Uniform Load Effective Address
10
ULEPC
Uniform Load Effective PC
2
ULOP3
Logic Operation
2
UMOV
Uniform Move
2
UP2UR
Uniform Predicate to Uniform Register
2
UPLOP3
Uniform Predicate Logic Operation
4
UPOPC
Uniform Population Count
2
UPRMT
Uniform Byte Permute
2
UR2UP
Uniform Register to Uniform Predicate
2
USEL
Uniform Select
2
USETMAXREG
Release, Deallocate and Allocate Registers
1
USETSHMSZ
Unknown op
unknown
USGXT
Uniform Sign Extend
2
USHF
Uniform Funnel Shift
3
UTMACCTL
TMA Cache Control
2
UTMACMDFLUSH
TMA Command Flush
1
UTMALDG
Tensor Load from Global to Shared Memory
4
UTMAPF
Tensor Prefetch
4
UTMAREDG
Tensor Store from Shared to Global Memory with Reduction
2
UTMASTG
Tensor Store from Shared to Global Memory
2
VABSDIFF
Absolute Difference
9
VABSDIFF4
Absolute Difference
9
VHMNMX
SIMD FP16 3-Input Minimum / Maximum
5
VIADD
SIMD Integer Addition
5
VIADDMNMX
SIMD Integer Addition and Fused Min/Max Comparison
9
VIMNMX
SIMD Integer Minimum / Maximum
5
VIMNMX3
SIMD Integer 3-Input Minimum / Maximum
5
VOTE
Vote Across SIMT Thread Group
1
VOTEU
Voting across SIMD Thread Group with Results in Uniform Destination
1
WARPGROUPSET
Set Warpgroup Counters
3

Unfound Instructions

Our fuzzer has not found these 66 instructions. If you have a cubin that contains any of these instructions and would like to contribute it, message us at collab@sf-tensor.com

BAR
Barrier Synchronization
unfound
BGMMA
Bit Matrix Multiply and Accumulate Across Warps
unfound
BMOV
Move Convergence Barrier State
unfound
BPT
BreakPoint/Trap
unfound
BRA
Relative Branch
unfound
BREAK
Break out of the Specified Convergence Barrier
unfound
BRX
Relative Branch Indirect
unfound
BRXU
Relative Branch with Uniform Register Based Offset
unfound
BSSY
Barrier Set Convergence Synchronization Point
unfound
BSYNC
Synchronize Threads on a Convergence Barrier
unfound
CALL
Call Function
unfound
CCTL
Cache Control
unfound
CCTLL
Cache Control
unfound
CCTLT
Texture Cache Control
unfound
DEPBAR
Dependency Barrier
unfound
EXIT
Exit Program
unfound
F2F
Floating Point To Floating Point Conversion
unfound
FADD32I
FP32 Add
unfound
FENCE
Memory Visibility Guarantee for Shared or Global Memory
unfound
FFMA32I
FP32 Fused Multiply and Add
unfound
FMUL32I
FP32 Multiply
unfound
HADD2_32I
FP16 Add
unfound
HFMA2_32I
FP16 Fused Mutiply Add
unfound
HGMMA
Matrix Multiply and Accumulate Across a Warpgroup
unfound
HMUL2_32I
FP16 Multiply
unfound
IADD
Integer Addition
unfound
IADD32I
Integer Addition
unfound
IDP4A
Integer Dot Product and Accumulate
unfound
IGMMA
Integer Matrix Multiply and Accumulate Across a Warpgroup
unfound
IMUL
Integer Multiply
unfound
IMUL32I
Integer Multiply
unfound
ISCADD
Scaled Integer Addition
unfound
ISCADD32I
Scaled Integer Addition
unfound
JMP
Absolute Jump
unfound
JMX
Absolute Jump Indirect
unfound
JMXU
Absolute Jump with Uniform Register Based Offset
unfound
KILL
Kill Thread
unfound
LDGMC
Reducing Load
unfound
LOP
Logic Operation
unfound
LOP32I
Logic Operation
unfound
MEMBAR
Memory Barrier
unfound
MOV32I
Move
unfound
NANOSLEEP
Suspend Execution
unfound
PSETP
Combine Predicates and Set Predicate
unfound
QGMMA
FP8 Matrix Multiply and Accumulate Across a Warpgroup
unfound
REDG
Reduction Operation on Generic Memory
unfound
RET
Return From Subroutine
unfound
SETLMEMBASE
Set Local Memory Base Address
unfound
SHL
Shift Left
unfound
SHR
Shift Right
unfound
ST
Store to Generic Memory
unfound
STG
Store to Global Memory
unfound
STL
Store to Local Memory
unfound
STS
Store to Shared Memory
unfound
STSM
Store Matrix to Shared Memory
unfound
SURED
Reduction Op on Surface Memory
unfound
SUST
Surface Store
unfound
UIADD3.64
Uniform Integer Addition
unfound
ULOP
Logic Operation
unfound
ULOP32I
Logic Operation
unfound
UPSETP
Uniform Predicate Logic Operation
unfound
USHL
Uniform Left Shift
unfound
USHR
Uniform Right Shift
unfound
WARPGROUP
Warpgroup Synchronization
unfound
WARPSYNC
Synchronize Threads in Warp
unfound
YIELD
Yield Control
unfound