NVIDIA ISA Viewer

REDUX

Reduction of a Vector Register into a Uniform Register

1 variant on SM90 (H100)

REDUX

UR,R

distilled: @P0 REDUX UR0, R0 ;

key: REDUX_UR_R

0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7
0	0	1	0	0	0	1	1	1	1	0	0	pred				operand 0							0	operand 1								0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7
0	0	0	0	0	0	0	0	0	S32	0	0	0	0	modi 2			0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	stall				y	r-bar			w-bar			b-mask						reuse				0	0

Modifier Group 1

Binary	Value
000	(default)
001	OR
010	XOR
011	SUM
100	MIN
101	MAX
110	INVALID6
111	INVALID7