CREDUX

Coupled Reduction of a Vector Register into a Uniform Register

1 variant on SM100 (Blackwell)

CREDUX

UR,R

distilled: @P0 CREDUX.MAX UR0, R0;

key: CREDUX_UR_R

0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7
0	0	1	1	0	0	1	1	0	1	0	0	pred				operand 0								operand 1								0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7
0	0	0	0	0	0	0	0	0	modi 1		0	0	NAN	modi 2		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	stall				y	r-bar			w-bar			b-mask						reuse				0	0

Modifier Group 1

Binary	Value
00	(default)
01	S32
10	F32
11	INVALID3

Modifier Group 2

Binary	Value
00	MAX
01	MAXABS
10	MIN
11	MINABS

Bit ranges are shown least-significant bit first.